text | un: CARCINOGENETICIST

[klawful]

THIS IS BIOLOGICAL FUCKING WARFARE.
THIS IS A COMPLETE DECONSTRUCTION OF BODILY AUTONOMY.
SOME MAY EVEN GO AS FAR AS TO SAY THIS IS AN ACTUAL HATE CRIME. FOR I, ABOVE ALL ELSE, FEEL ESPECIALLY HATED RIGHT NOW.
THIS IS A HEINOUS ACT OF THE HIGHEST CALIBER AND THERE WILL BE GREAT RETRIBUTION, MARK MY WORD.

DO NOT ASK ME WHAT THIS IS ABOUT AS IT IS NONE OF YOUR FUCKING BUSINESS. I JUST WANTED TO ANNOUNCE MY DISSATISFACTION WITH THE CURRENT SITUATION TO THE WORLD AND SOCIAL MEDIA IS A VALID FORM OF PUBLIC DESPAIR. IF YOU DISAGREE I HAVE AN INCREDIBLY SPECIFIC PLACE WHERE YOU CAN "SHOVE IT" AS THEY SAY. MY DESPAIR IS CERTIFIABLE AND THIS DEERNET PLACE IS NOW MY PARTY WHERE I CAN FUCKING CRY IF I WANT TO.

NOT THAT I AM CRYING. THAT WOULD BE FOR SOMEONE EMOTIONALLY WEAKER THAN I, WHICH I HAVE NEVER BEEN EMOTIONALLY WEAK AT A SINGLE MOMENT IN MY ENTIRE LIFESPAN.

IF YOU DISLIKE IT, THEN YOU CAN FUCKING BLOCK ME AND GET OVER YOURSELF IN YOUR OWN CORNER OF THE INTERNET. EAT MY ENTIRE FUCKING BULGE. EXCEPT DO NOT. TO BE CLEAR, THAT WAS NOT A COME-ON OF ANY KIND. I WILL BURY YOU IN THE MISERABLE SANDS FROM WHICH WE HAVE BEEN REINCARNATED AND YOU WILL NOT REAWAKEN. FOR I WILL BE STANDING THERE TO CUT YOU DOWN THE MOMENT YOU OPEN YOUR EYES. SO, LITERALLY, YOU WILL NOT SEE IT AGAIN. THEORETICALLY. I CANNOT ACTUALLY TRULY ANTICIPATE THE EXACT SECOND YOU OPEN YOUR EYES BUT I WILL BE PREPARED ALL THE SAME.

*I WILL NOT BE CENSORED.*

Comments

i am so sorry. do not actually read those chunks of text ur eyes will glaze

[klawful]

NO WHY DO PEOPLE KEEP SAYING THAT SHIT. WHAT IS EVERYONE'S DEFINITION OF "ART" IF THIS IS WHAT YOU COME UP WITH?
I MEAN, I AM A TROLL, YES, BUT I HAVE A HUNCH YOU ARE USING THAT IN THE DEROGATORY SENSE RATHER THAN THE LITERAL SENSE IN WHICH CASE FUCK YOU, BUT ALSO YES.

WHAT THE FUCK IS "ALT-RIGHT"

YEAH, YOU DO. LEARN TO READ, BITCH.
NO, BECAUSE THEN I WOULD MISS SAYING SOMETHING EXTREMELY WORTH SAYING. AND BEING CONCISE IS FOR DIPSHITS WHO HAVE NOTHING INTERESTING TO SAY AND LIKE TO THINK THEY'RE PUTTING ON AN AURA OF BEING ~*MYSTERIOUS*~ WHEN REALLY THEY ARE JUST CONVERSATIONALLY FLACCID AND BORING AS FUCK. NO WAY.

IF ANYTHING I SHOULD TYPE MUCH SMALLER AND START QUOTING ENTIRE PASSAGES OF LITERATURE LITERALLY NO ONE GIVES A FUCK ABOUT SUCH AS THIS WIKIPEDIA PAGE ABOUT VERY LONG INSTRUCTION WORD:

"In superscalar designs, the number of execution units is invisible to the instruction set. Each instruction encodes one operation only. For most superscalar designs, the instruction width is 32 bits or fewer.

In contrast, one VLIW instruction encodes multiple operations, at least one operation for each execution unit of a device. For example, if a VLIW device has five execution units, then a VLIW instruction for the device has five operation fields, each field specifying what operation should be done on that corresponding execution unit. To accommodate these operation fields, VLIW instructions are usually at least 64 bits wide, and far wider on some architectures.

For example, the following is an instruction for the Super Harvard Architecture Single-Chip Computer (SHARC). In one cycle, it does a floating-point multiply, a floating-point add, and two autoincrement loads. All of this fits in one 48-bit instruction:

f12 = f0 * f4, f8 = f8 + f12, f0 = dm(i0, m3), f4 = pm(i8, m9);

Since the earliest days of computer architecture,[1] some CPUs have added several arithmetic logic units (ALUs) to run in parallel. Superscalar CPUs use hardware to decide which operations can run in parallel at runtime, while VLIW CPUs use software (the compiler) to decide which operations can run in parallel in advance. Because the complexity of instruction scheduling is moved into the compiler, complexity of hardware can be reduced substantially.[clarification needed]

A similar problem occurs when the result of a parallelizable instruction is used as input for a branch. Most modern CPUs guess which branch will be taken even before the calculation is complete, so that they can load the instructions for the branch, or (in some architectures) even start to compute them speculatively. If the CPU guesses wrong, all of these instructions and their context need to be flushed and the correct ones loaded, which takes time.

This has led to increasingly complex instruction-dispatch logic that attempts to guess correctly, and the simplicity of the original reduced instruction set computing (RISC) designs has been eroded. VLIW lacks this logic, and thus lacks its energy use, possible design defects, and other negative aspects.

In a VLIW, the compiler uses heuristics or profile information to guess the direction of a branch. This allows it to move and preschedule operations speculatively before the branch is taken, favoring the most likely path it expects through the branch. If the branch takes an unexpected way, the compiler has already generated compensating code to discard speculative results to preserve program semantics.

Vector processor (single instruction, multiple data (SIMD)) cores can be combined with the VLIW architecture such as in the Fujitsu FR-V microprocessor, further increasing throughput and speed."

WOW ISN'T THAT AMAZING.

HERE'S ANOTHER ONE ON THE ARTICLE ABOUT "SIMULTANEOUS MULTITHREADING" RIVETING STUFF, I KNOW:

"The Intel Pentium 4 was the first modern desktop processor to implement simultaneous multithreading, starting from the 3.06 GHz model released in 2002, and since introduced into a number of their processors. Intel calls the functionality Hyper-Threading Technology, and provides a basic two-thread SMT engine. Intel claims up to a 30% speed improvement[4] compared against an otherwise identical, non-SMT Pentium 4. The performance improvement seen is very application-dependent; however, when running two programs that require full attention of the processor it can actually seem like one or both of the programs slows down slightly when Hyper-threading is turned on.[5] This is due to the replay system of the Pentium 4 tying up valuable execution resources, increasing contention for resources such as bandwidth, caches, TLBs, re-order buffer entries, equalizing the processor resources between the two programs which adds a varying amount of execution time. The Pentium 4 Prescott core gained a replay queue, which reduces execution time needed for the replay system. This is enough to completely overcome that performance hit.[6]

The latest Imagination Technologies MIPS architecture designs include an SMT system known as "MIPS MT".[7] MIPS MT provides for both heavyweight virtual processing elements and lighter-weight hardware microthreads. RMI, a Cupertino-based startup, is the first MIPS vendor to provide a processor SOC based on eight cores, each of which runs four threads. The threads can be run in fine-grain mode where a different thread can be executed each cycle. The threads can also be assigned priorities. Imagination Technologies MIPS CPUs have two SMT threads per core.

IBM's Blue Gene/Q has 4-way SMT.

The IBM POWER5, announced in May 2004, comes as either a dual core dual-chip module (DCM), or quad-core or oct-core multi-chip module (MCM), with each core including a two-thread SMT engine. IBM's implementation is more sophisticated than the previous ones, because it can assign a different priority to the various threads, is more fine-grained, and the SMT engine can be turned on and off dynamically, to better execute those workloads where an SMT processor would not increase performance. This is IBM's second implementation of generally available hardware multithreading. In 2010, IBM released systems based on the POWER7 processor with eight cores with each having four Simultaneous Intelligent Threads. This switches the threading mode between one thread, two threads or four threads depending on the number of process threads being scheduled at the time. This optimizes the use of the core for minimum response time or maximum throughput. IBM POWER8 has 8 intelligent simultaneous threads per core (SMT8).

IBM Z starting with the z13 processor in 2013 has two threads per core (SMT-2).

Although many people reported that Sun Microsystems' UltraSPARC T1 (known as "Niagara" until its 14 November 2005 release) and the now defunct processor codenamed "Rock" (originally announced in 2005, but after many delays cancelled in 2010) are implementations of SPARC focused almost entirely on exploiting SMT and CMP techniques, Niagara is not actually using SMT. Sun refers to these combined approaches as "CMT", and the overall concept as "Throughput Computing". The Niagara has eight cores, but each core has only one pipeline, so actually it uses fine-grained multithreading. Unlike SMT, where instructions from multiple threads share the issue window each cycle, the processor uses a round robin policy to issue instructions from the next active thread each cycle. This makes it more similar to a barrel processor. Sun Microsystems' Rock processor is different, it has more complex cores that have more than one pipeline.

The Oracle Corporation SPARC T3 has eight fine-grained threads per core, SPARC T4, SPARC T5, SPARC M5, M6 and M7 have eight fine-grained threads per core of which two can be executed simultaneously.

Fujitsu SPARC64 VI has coarse-grained Vertical Multithreading (VMT) SPARC VII and newer have 2-way SMT.

Intel Itanium Montecito used coarse-grained multithreading and Tukwila and newer use 2-way SMT (with dual-domain multithreading).

Intel Xeon Phi has 4-way SMT (with time-multiplexed multithreading) with hardware-based threads which can't be disabled unlike regular Hyperthreading.[8] The Intel Atom, released in 2008, is the first Intel product to feature 2-way SMT (marketed as Hyper-Threading) without supporting instruction reordering, speculative execution, or register renaming. Intel reintroduced Hyper-Threading with the Nehalem microarchitecture, after its absence on the Core microarchitecture.

AMD Bulldozer microarchitecture FlexFPU and Shared L2 cache are multithreaded but integer cores in module are single threaded, so it is only a partial SMT implementation.[9][10]

AMD Zen microarchitecture has 2-way SMT.

VISC architecture[11][12][13][14] uses the Virtual Software Layer (translation layer) to dispatch a single thread of instructions to the Global Front End which splits instructions into virtual hardware threadlets which are then dispatched to separate virtual cores. These virtual cores can then send them to the available resources on any of the physical cores. Multiple virtual cores can push threadlets into the reorder buffer of a single physical core, which can split partial instructions and data from multiple threadlets through the execution ports at the same time. Each virtual core keeps track of the position of the relative output. This form of multithreading can increase single threaded performance by allowing a single thread to use all resources of the CPU. The allocation of resources is dynamic on a near-single cycle latency level (1–4 cycles depending on the change in allocation depending on individual application needs. Therefore, if two virtual cores are competing for resources, there are appropriate algorithms in place to determine what resources are to be allocated where."

OKAY, THIS IS EXCESSIVE EVEN FOR ME. I ALREADY REGRET POSTING THIS BUT I HAVE TO COMMIT TO MY MISTAKES TO TRULY LEARN FROM THEM.

1/2

[hauntedsavior]

[✓ Read.]

[hauntedsavior]

[and, several minutes later.]

This might actually be the funniest thing that has ever happened to me.
Whatever the fuck you are, little dude, keep doing it.

[klawful]

(Well shit.)

I AM NOT LITTLE AT ALL. I AM OBJECTIVELY BIG WHEN COMPARED TO CERTAIN SENTIENT LIFE FORMS. I AM EVEN A GIANT TO SOME. LIKE INSECTS.

I AM SORRY THAT YOUR LIFE WILL BE BLEAK FROM THIS POINT FORWARD AND THAT NO ONE WILL EVER BRING YOU THE AMUSEMENT AND JOY I JUST DID.

[hauntedsavior]

Dude, you are the weirdest troll I've ever met.
Never seen someone brag about their height so openly? Like, you threw shitload of conditionals on that one.
Maybe next time just say something like "I'm seven feet tall" or "ur mom suck me good and hard thru my jorts".

[klawful]

YOU HAVE NO FUCKING IDEA HOW ACCURATE THAT STATEMENT ACTUALLY IS.

WHY WOULD I WANT YOUR DISGUSTING MOTHER TO STUCK ANY PART OF ME? I ONLY ALLOW SUCKINGS FROM ABSOLUTE BABES AND THERE IS NO WAY ANY PART OF YOUR GENETIC POOL IS DEEMED ATTRACTIVE.

[hauntedsavior]

Damn, dude, tell me how you really feel about who gets to suck you off.
Better make sure the next time you pull that genetic pool line, you're talking to someone who has genes.